Journal Articles
International Conference
Domestic Conference
Supervised Thesis
 

 

 

 
 

Journal Articles & Book Chapters

  • Hao-Yu Chi, Zi-Jun Lin, Chia-Hao Hung, Chien-Nan Jimmy Liu, and Hung-Ming Chen, "A Style-based Analog Layout Migration Technique with Complete Routing Behavior Preservation", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (SCI, EI), vol. 40, no. 12, pp. 2556-2567, December 2021.
  • Ling-Yen Song, Yu-Kang Lou, Ching-Ho Lin, Chien-Nan Liu, Juinn-Dar Huang, Jing-Yang Jou, Meng-Jung Lee, and Yu-Lan Lo, "Efficient Circuit Structure Analysis for Automatic Behavioral Model Generation in Mixed-Signal System Simulation", MDPI Electronics (SCI), vol. 10, issue 9, article 1088, May 2021.
  • Hao-Yu Chi, Chien-Nan Jimmy Liu, and Hung-Ming Chen, "Wire Load Oriented Analog Routing with Matching Constraints", ACM Transactions on Design Automation of Electronic Systems (SCI, EI), vol. 25, no. 6, article 55, August 2020.
  • Tai-Hung Li, Jwu-E Chen, Tai-Chen Chen and Chien-Nan Jimmy Liu, "Modelling and optimisation algorithm for length-matching escape routing of differential pairs", IET Electronics Letters (SCI, EI), vol. 55, issue 10, pp. 603-605, May 2019.
  • Nguyen Cao Qui, Si-Rong He, and Chien-Nan Jimmy Liu, "An Incremental Simulation Technique Based on Delta Model for Lifetime Yield Analysis", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (SCI, EI), vol. E100-A, no. 11, pp. 2370-2378, November 2017.
  • Nguyen Cao Qui, Si-Rong He, and Chien-Nan Jimmy Liu, "Cluster-Based Delta-QMC Technique for Fast Yield Analysis", Integration, the VLSI Journal, Elsevier (SCI, EI), vol. 58, pp. 64-73, June 2017.
  • Chien-Nan Jimmy Liu, Yen-Lung Chen, and Nguyen Cao Qui, "Automated Robust Design Optimization of Analog Circuits for Flexible Electronics", Flexible and Wearable Electronics: Design and Fabrication Techniques, United Scholars Publications (ISBN:978-0692751718), pp. 33-72, August 2016.
  • Wen-En Wei, Hung-Yi Li, Cheng-Yu Han, James Chien-Mo Li, Jian-Jang Huang, I-Chun Cheng, Chien-Nan Liu, and Yung-Hui Yeh, "A Flexible TFT Circuit Yield Optimizer Considering Process Variation, Aging, and Bending Effects", IEEE/OSA Journal of Display Technology (SCI, EI), vol. 10, no. 12, pp. 1055-1063, December 2014.
  • Yen-Lung Chen and Chien-Nan Jimmy Liu, "A Unified Analog Synthesis Approach Considering Parasitic Effects and Process Variations", Performance Optimization Techniques in Analog, Mixed-Signal, and Radio-Frequency Circuit Design, IGI Global (ISBN:978-1-4666-6627-6), pp. 55-70, October 2014.
  • Yen-Lung Chen, Wan-Rong Wu, Chien-Nan Jimmy Liu, and James Chien-Mo Li, "Simultaneous Optimization of Analog Circuits with Reliability and Variability for the Applications on Flexible Electronics", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (SCI, EI), vol. 33, no. 1, pp. 24-35, January 2014.
  • Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu, and Wen-Yu Shih, "Package Routability- and IR-Drop-Aware Finger/Pad Planning for Single Chip and Stacking IC Designs", Integration, the VLSI Journal, Elsevier (SCI, EI), vol. 46, no. 3, pp. 280-289, June 2013.
  • Chien-Nan Jimmy Liu, Yen-Lung Chen, Chin-Cheng Kuo and I-Ching Tsai, "A Fast Heuristic Approach for Parametric Yield Enhancement of Analog Designs", ACM Transactions on Design Automation of Electronic Systems (SCI, EI), vol. 17, no. 3, article 35, June 2012.
  • Mu-Shun Matt Lee, Wei-Ting Liao and Chien-Nan Jimmy Liu, "Levelized High-Level Current Model of Logic Blocks for Dynamic Supply Noise Analysis", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (SCI, EI), vol. 31, no. 6, pp. 845-857, June 2012.
  • Mu-Shun Matt Lee and Chien-Nan Jimmy Liu, "Library-Based Gate-Level Current Waveform Modeling for Dynamic Supply Noise Analysis", VLSI Design, InTech (ISBN:978-953-307-884-7), pp.183-208, January 2012.
  • Chin-Lung Chuang and Chien-Nan Jimmy Liu, "Hybrid Testbench Acceleration for Reducing Communication Overhead", IEEE Design & Test of Computers (SCI, EI), vol. 28, no. 2, pp. 40-50, March 2011.
  • Chao-Hung Lu, Hung-Ming Chen, and Chien-Nan Jimmy Liu, "Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits", Journal of Information Science and Engineering (SCI, EI), vol. 27, no. 1, pp. 287-302, January 2011.
  • Yuhwai Tseng, Chauchin Su, and Chien-Nan Jimmy Liu, "Measurement and Evaluation of the Bioelectrical Impedance of the Human Body Using Deconvolution of a Square Wave", IEICE Transactions on Information and Systems (SCI, EI), vol. E93-D, no. 6, pp. 1656-1660, June 2010.
  • Mu-Shun Matt Lee and Chien-Nan Jimmy Liu, "Dynamic Supply Current Waveform Estimation with Standard Library Information", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (SCI, EI), vol. E93-A, no. 3, pp. 595-606, March 2010.
  • Yuhwai Tseng, Chauchin Su, and Chien-Nan Jimmy Liu, "Measuring the Transmission Characteristic of the Human Body in an Electrostatic-Coupling Intra Body Communication System using a Square Test Stimulus", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (SCI, EI), vol. E93-A, no. 3, pp. 664-668, March 2010.
  • Chin-Cheng Kuo and Chien-Nan Jimmy Liu, "Fast and Accurate Analysis of Supply Noise Effects in PLL with Noise Interactions", IEEE Transactions on Circuits and Systems I (SCI, EI), vol. 57, no. 1, pp. 44-52, January 2010.
  • Yuhwai Tseng, Chauchin Su, and Chien-Nan Jimmy Liu, "Analysis and Design of Wide-Band Digital Transmission in an Electrostatic-Coupling Intra-Body Communication System", IEICE Transactions on Communications (SCI, EI), vol. E92-B, no. 11, pp. 3557-3563, November 2009.
  • Hungwen Lu, Hsin-Wen Wang, Chauchin Su, and Chien-Nan Jimmy Liu, "Design of an All-Digital LVDS Driver", IEEE Transactions on Circuits and Systems I (SCI, EI), vol. 56, no. 8, pp. 1635-1644, August 2009.
  • Kuo-Hsing Cheng, Yu-Chang Tsai, Chien-Nan Jimmy Liu, Kai-Wei Hong, and Chin-Cheng Kuo, "A Low Jitter Self-Calibration PLL for 10-Gbps SoC Transmission Links Application", IEICE Transactions on Electronics (SCI, EI), vol. E92-C, no. 7, pp. 964-972, July 2009.
  • Chin-Cheng Kuo, Meng-Jung Lee, Chien-Nan Jimmy Liu, and Ching-Ji Huang, "Fast Statistical Analysis of Process Variation Effects Using Accurate PLL Behavioral Models", IEEE Transactions on Circuits and Systems I (SCI, EI), vol. 56, no. 6, pp. 1160-1172, June 2009.
  • Chih-Hu Wang, Chun-Hung Lin, Bore-Kuen Lee, Chien-Nan Jimmy Liu, and Chauchin Su, "Adaptive Two-Stage Fuzzy Temperature Control for an Electroheat System", International Journal of Fuzzy Systems, (SCI-E, EI), vol. 11, no. 1, pp. 59-66, March 2009.
  • Tai-Ying Jiang, Chien-Nan Jimmy Liu, and Jing-Yang Jou, "Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (SCI, EI), vol. 28, no. 2, pp. 272-284, February 2009.
  • Hungwen Lu, ChauChin Su, and Chien-Nan Jimmy Liu, "A Tree-Topology Multiplexer for Multiphase Clock System", IEEE Transactions on Circuits and Systems I (SCI, EI), vol. 56, no. 1, pp. 124-131, January 2009.
  • Chih-Hu Wang, Bor-Sen Chen, Bore-Kuen Lee, Tsu-Tian Lee, Chien-Nan Jimmy Liu, and Chauchin Su, "Long-Range Prediction for Real-Time MPEG Video Traffic: An H∞ Filter Approach", IEEE Transactions on Circuits and Systems for Video Technology (SCI, EI), vol. 18, no. 12, pp. 1771-1775, December 2008.
  • Hungwen Lu, ChauChin Su, and Chien-Nan Liu, "A Scalable Digitalized Buffer for Gigabit I/O", IEEE Transactions on Circuits and Systems II (SCI, EI), vol. 55, no. 10, pp. 1026-1030, October 2008.
  • Chao-Hung Lu, Hung-Ming Chen, and Chien-Nan Jimmy Liu, "Effective Decap Insertion in Area-Array SoC Floorplan Design", ACM Transactions on Design Automation of Electronic Systems (SCI, EI), vol. 13, no. 4, article 66, September 2008.
  • Chao-Hung Lu, Hung-Ming Chen, and Chien-Nan Jimmy Liu, "An Effective Decap Insertion Method Considering Power Supply Noise During Floorplanning", Journal of Information Science and Engineering (SCI, EI), vol. 24, no. 1, pp. 115-127, January 2008.
  • Tai-Ying Jiang, Chien-Nan Jimmy Liu, and Jing-Yang Jou, "Observability Analysis on HDL Descriptions for Effective Functional Validation", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (SCI, EI), vol. 26, no. 8, pp. 1509-1521, August 2007.
  • Wen-Tsan Hsieh, Chi-Chia Yu, Chien-Nan Jimmy Liu, and Yi-Fang Chiu, "An Efficient Approach with Scaling Capability to Improve Existing Memory Power Model", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (SCI, EI), vol. E90-A, no. 5, pp. 1038-1044, May 2007.
  • Chin-Lung Chuang, Wei-Hsiang Cheng, Dong-Jung Lu, and Chien-Nan Jimmy Liu, "Hybrid Approach to Faster Functional Verification with Full Visibility", IEEE Design & Test of Computers (SCI, EI), vol. 24, no. 2, pp. 154-162, March 2007.
  • Chih-Yang Hsu, Wen-Tsan Hsieh, Chien-Nan Jimmy Liu, and Jing-Yang Jou, "A Tableless Approach for High-Level Power Modeling Using Neural Networks", Journal of Information Science and Engineering (SCI, EI), vol. 23, no. 1, pp.71-90, January 2007.
  • Wenliang Tseng, Chien-Nan Jimmy Liu, and Chauchin Su, "Passive Reduced-order Macromodeling for Linear Time-delay Interconnect systems", IEICE Transactions on Electronics (SCI, EI), vol. E89-C, no. 11, Nov. 2006.
  • Wen-Tsan Hsieh, Chih-Chieh Shiue, and Chien-Nan Jimmy Liu, "Efficient Power Modeling Approach of Sequential Circuits Using Recurrent Neural Networks", IEE Proceedings - Computers and Digital Techniques (SCI, EI), vol. 153, no. 2, pp. 78-86, March 2006.
  • Chin-Cheng Kuo, Yu-Chien Wang, and Chien-Nan Jimmy Liu, "An Efficient Approach to Build Accurate PLL Behavioral Models of PLL Designs", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (SCI, EI), vol. E89-A, no. 2, pp. 391-398, February 2006.
  • Chien-Nan Jimmy Liu, "A Design-for-Verification Technique for Debugging HDL Designs", International Journal of Electrical Engineering (EI), vol. 12, no. 1, pp. 99-104, February 2005.
  • Chih-Yang Hsu, Chien-Nan Jimmy Liu, and Jing-Yang Jou, "Efficient Vector Compaction Methods for Power Estimation with Consecutive Sampling Techniques ", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (SCI, EI), vol. E87-A, no. 11, pp. 2973-2982, November 2004.
  • Chih-Yang Hsu, Chien-Nan Jimmy Liu, and Jing-Yang Jou, "An Efficient Power Model for IP-Level Complex Designs ", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (SCI, EI), vol. E86-A, no. 8, pp. 2073-2080, August 2003.
  • Chien-Nan Jimmy Liu, I-Ling Chen, and Jing-Yang Jou, "A Design-for-Verification Technique for Functional Pattern Reduction ", IEEE Design & Test of Computers (SCI, EI), vol. 20, no. 2, pp. 48-55, March 2003.
  • C.-N. Liu and J.-Y. Jou, "Efficient Coverage Analysis Metric for HDL Design Validation", IEE Proceedings - Computers and Digital Techniques (SCI, EI), vol. 148, no.1, pp. 1-6, January 2001.
  • Chien-Nan Jimmy Liu and Jing-Yang Jou, "An Automatic Controller Extractor for HDL Descriptions at RTL", IEEE Design & Test of Computers (SCI, EI), vol. 17, no. 3, pp. 72-77, September 2000.
  • International Conference Proceedings

  • Shih-Han Chang, Chien-Nan Jimmy Liu and Alexandra Küster, "Behavioral Level Simulation Framework to Support Error-Aware CNN Training with In-Memory Computing", accepted to appear in IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), June 2022.
  • Cheng-Yu Chiang, Chia-Lin Hu, Mark Po-Hung Lin, Kang-Yu Chang, Shyh-Jye Jou, Chien-Nan Liu and Hung-Ming Chen, "On Optimizing Capacitor Array Design for Advanced Node SAR ADC", accepted to appear in IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), June 2022.
  • Bo-Cheng Lai, Tzu-Chieh Chiang, Po-Shen Kuo, Wan-Ching Wang, Yan-Lin Hung, Hung-Ming Chen, Chien-Nan Liu and Shyh-Jye Jou, "DASC : A DRAM Data Mapping Methodology for Sparse Convolutional Neural Networks", IEEE/ACM Design, Automation & Test in Europe (DATE) (EI), March 2022.
  • Hao-Yu Chi, Yi-Hung Simon Chen, Hung-Ming Chen, Chien-Nan Liu, Yun-Chih Kuo, Ya-Hsin Chang and Kuan-Hsien Ho, "Practical Substrate Design Considering Symmetrical and Shielding Routes", IEEE/ACM Design, Automation & Test in Europe (DATE) (EI), March 2022.
  • Ling-Yen Song, Tung-Chieh Kuo, Ming-Hung Wang, Chien-Nan Jimmy Liu and Juinn-Dar Huang, "Fast Variation-aware Circuit Sizing Approach for Analog Design with ML-Assisted Evolutionary Algorithm", ACM/IEEE Asia and South Pacific Design Automation Conference (EI), January 2022.
  • Hung-Ming Chen, Cheng-En Ni, Kang-Yu Chang, Tzu-Chieh Chiang, Shih-Han Chang, Cheng-Yu Chiang, Bo-Cheng Lai, Chien-Nan Liu and Shyh-Jye Jou, "On Reconfiguring Memory-Centric AI Edge Devices for CIM", IEEE International SOC Design Conference, October 2021.
  • Ling-Yen Song, Chih-Shen Yeh, Chien-Nan Liu and Juinn-Dar Huang, "Storage-Aware Scheduling Algorithm for Reservoir Switching Minimization on Digital Microfluidic Biochips", IEEE International Symposium on VLSI Design, Automation, and Test (EI), April 2021. (Best Paper Award)
  • Hao-Yu Chi, Han-Chung Chang, Chih-Hsin Yang, Chien-Nan Jimmy Liu, and Jing-Yang Jou, "Performance-driven Routing Methodology with Incremental Placement Refinement for Analog Layout Design", IEEE/ACM Design, Automation & Test in Europe (DATE) (EI), February 2021.
  • Mark Po-Hung Lin, Hao-Yu Chi, Abhishek Patyal, Zheng-Yao Liu, Jun-Jie Zhao, Chien-Nan Jimmy Liu, and Hung-Ming Chen, "Achieving Analog Layout Integrity through Learning and Migration", IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (EI), November 2020.
  • Hung-Ming Chen, Chia-Lin Hu, Kang-Yu Chang, Alexandra Küster, Yu-Hsien Lin, Po-Shen Kuo, Wei-Tung Chao, Bo-Cheng Lai, Chien-Nan Liu, and Shyh-Jye Jou, "On EDA Solutions for Reconfigurable Memory-Centric AI Edge Applications", IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (EI), November 2020.
  • Hao-Yu Chi, Zi-Jun Lin, Chia-Hao Hung, Chien-Nan Jimmy Liu, and Hung-Ming Chen, "Achieving Routing Integrity in Analog Layout Migration via Cartesian Detection Lines", IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (EI), November 2019.
  • Hsin-Ju Hsu, Ji-Xuan Tsai, Meng-Lin Li,Chien-Nan Jimmy Liu, and Jing-Yang Jou, "FPGA Implementation for WDF-Based Analog Emulator with Complicated Topology", the 22nd Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), October 2019.
  • Yu-Hsien Chen, Hao-Yu Chi, Ling-Yen Song, Chien-Nan Jimmy Liu, and Hung-Ming Chen, "A Structure-Based Methodology for Analog Layout Generation", IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), July 2019.
  • Hsin-Ju Hsu, Wan-Chun Chen, Long-Ching Yeh and Chien-Nan Jimmy Liu, "Spec-to-Layout Automation Flow for Buck Converters with Current-Mode Control in SOC Applications", IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), July 2018.
  • Abhishek Patyal, Po-Cheng Pan, Asha K A, Hung-Ming Chen, Hao-Yu Chi and Chien-Nan Liu, "Analog Placement with Current Flow and Symmetry Constraints using PCP-SP", IEEE/ACM Design Automation Conference (DAC) (EI), June 2018.
  • Loo Shean Liu, Hsin-Ju Hsu, Hao-Yu Chang, Chien-Nan Jimmy Liu, and Jing-Yang Jou, "Hardware Implementation of WDF-Based Analog Circuit Emulation", the 21st Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), March 2018.
  • Hao-Yu Chi, Hwa-Yi Tseng, Chien-Nan Jimmy Liu, and Hung-Ming Chen, "Performance-Preserved Analog Routing Methodology via Wire Load Reduction", ACM/IEEE Asia and South Pacific Design Automation Conference (EI), January 2018.
  • Si-Rong He, Nguyen Cao Qui, Yu-Hsuan Kuo, and Chien-Nan Jimmy Liu, "An Incremental Aging Analysis Method Based on Delta Circuit Simulation Technique", IEEE Asia Test Symposium (EI), November 2017.
  • Ling-Yen Song, Chun Wang, Chien-Nan Jimmy Liu, Yun-Jing Lin, Meng-Jung Lee, Yu-Lan Lo, Shu-Yi Kao, "Non-Regression Approach for the Behavioral Model Generator in Mixed-Signal System Verification", IEEE International Conference on Very Large Scale Integration (VLSI-SoC), October 2017.
  • Chih-Wei Lee, Hwa-Yi Tseng, Chi-Lien Kuo, Chien-Nan Jimmy Liu, and Chin Hsia, "Layout Placement Optimization with Isolation Rings for High-Voltage VLSI Circuits", IEEE International Symposium on VLSI Design, Automation, and Test (EI), April 2017.
  • Yo-Hao Tu, Kai-Wen Yao, Ming-Hao Huang, Yu-Yun Lin, Hao-Yu Chi, Po-Min Cheng, Pei-Yun Tsai, Muh-Tian Shiue, Chien-Nan Liu, Kuo-Hsing Cheng and Jia-Shiang Fu, "A Body Sensor Node SoC for ECG/EMG Applications with Compressed Sensing and Wireless Powering", IEEE International Symposium on VLSI Design, Automation, and Test (EI), April 2017.
  • Hsu-Ping Yang, Hsin-Ju Hsu, Chun Wang, Chien-Nan Jimmy Liu, and Jing-Yang Jou, "Automatic Netlist Transformation for WDF-Based Analog Emulator", the 20th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), October 2016. (IEEE CEDA SASIMI Young Researcher Award)
  • Wei Wu, Yen-Lung Chen, Yue Ma, Chien-Nan Liu, Jing-Yang Jou, Sudhakar Pamarti, and Lei He, "Wave Digital Filter based Analog Circuit Emulation on FPGA", IEEE International Symposium on Circuit and Systems (EI), May 2016.
  • Fang-Yu Jhou, Chang-Han Wang, Tsung-Yueh Wu, Yu-Kang Lou, and Chien-Nan Jimmy Liu, "Automatic Synthesis Flow for Voltage Rectifiers with Impedance Consideration", IEEE International Symposium on VLSI Design, Automation, and Test (EI), April 2016.
  • Chien-Nan Jimmy Liu, Yen-Lung Chen, Tsung-Yu Liu, and Tai-Chen Chen, "Reliability-Aware Design Automation Flow for Analog Circuits", IEEE International SOC Design Conference, November 2015. (Invited Paper)
  • Jian-Yu Chen, Shiou-Wen Wang, Ching-Ho Lin, Chien-Nan Liu, Yun-Jing Lin, Meng-Jung Lee, You-Lan Luo, Shu-Yi Kao, "Automatic Behavioral Model Generator for Mixed-Signal Circuits Based on Structure Recognition and Auto-Calibration", IEEE International SOC Design Conference, November 2015. (Synopsys Best Paper Award)
  • Ying-Chi Lien, Ching-Mao Lee, Chih-Wei Li, Ban-Han Tsai, and Chien-Nan Jimmy Liu, "Low-Noise Analog Synthesis Platform for Bio-signal Acquisition System", IEEE International Symposium on VLSI Design, Automation, and Test (EI), April 2015.
  • Hsin-Ju Chang, Yen-Lung Chen, Conan Yeh, and Chien-Nan Jimmy Liu, "Layout-aware Analog Synthesis Environment with Yield Consideration", IEEE International Symposium on Quality Electronic Design, March 2015.
  • Yen-Lung Chen, Wei Wu, Chien-Nan Jimmy Liu, and Lei He, "Incremental Latin Hypercube Sampling for Lifetime Stochastic Behavioral Modeling of Analog Circuits", ACM/IEEE Asia and South Pacific Design Automation Conference (EI), January 2015.
  • Yen-Lung Chen, Wei Wu, Lei He and Chien-Nan Jimmy Liu, "Stochastic Behavioral Modeling of Analog Circuits with Reliability and Variability for the Applications on Flexible Electronics", IEEE/ACM Design Automation Conference (DAC, WIP session) (EI), June 2014.
  • Hsing-Han Tseng, Shiou-Wen Wang, Jian-Yu Chen, and Chien-Nan Jimmy Liu, "A Novel Design Space Reduction Method for Efficient Simulation-Based Optimization", IEEE International Symposium on Circuit and Systems (EI), May 2014.
  • Yen-Lung Chen, Guan-Ming Chu, Ying-Chi Lien, Ching-Mao Lee, and Chien-Nan Jimmy Liu, "Simultaneous Optimization for Low Dropout Regulator and Its Error Amplifier with Process Variation", IEEE International Symposium on VLSI Design, Automation, and Test (EI), April 2014.
  • Ju-Chi Hsu, Mu-Shun Matt Lee, Shiou-Wen Wang, and Chien-Nan Jimmy Liu, "Dynamic Simultaneous Switching Noise Analysis with Advanced Standard Library Information", Asia-Pacific Radio Science Conference, September 2013.
  • Yu-Ching Liao, Yen-Lung Chen, Xian-Ting Cai, Chien-Nan Jimmy Liu, and Tai-Chen Chen, "LASER - Layout-aware Analog Synthesis Environment on Laker", ACM/IEEE Great Lakes Symposium on VLSI (EI), May 2013.
  • Yen-Lung Chen, Yi-Ching Ding, Yu-Ching Liao, Hsin-Ju Chang, and Chien-Nan Jimmy Liu, "A Layout-Aware Automatic Sizing Approach for Retargeting Analog Integrated Circuits", IEEE International Symposium on VLSI Design, Automation, and Test (EI), April 2013.
  • Yen-Lung Chen, Wan-Rong Wu, Guan-Ruei Lu, and Chien-Nan Jimmy Liu, "Automatic Circuit Sizing Technique for the Analog Circuits with Flexible TFTs Considering Process Variation and Bending Effects", IEEE/ACM Design, Automation & Test in Europe (DATE) (EI), March 2013.
  • Kai-Hui Chang, Chia-Wei Chang, Jie-Hong Roland Jiang, and Chien-Nan Jimmy Liu, "Reducing Test Point Overhead with Don't-Cares", IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), August 2012.
  • Ya-Fang Cheng, Li-Yu Chan, Yen-Lung Chen, Yu-Ching Liao, and Chien-Nan Jimmy Liu, "A Bias-Driven Approach to Improve the Efficiency of Automatic Design Optimization for CMOS OP-Amps", IEEE Asia Symposium on Quality Electronic Design (ASQED), July 2012.
  • Kai-Hui Chang, Chia-Wei Chang, Jie-Hong Roland Jiang, and Chien-Nan Jimmy Liu, "Improving Design Verifiability by Early RTL Coverability Analysis", ACM/IEEE International Conference on Formal Methods and Models for Codesign, July 2012.
  • Yen-Lung Chen, Yi-Ching Ding, Yun-Jing Lin, and Chien-Nan Jimmy Liu, "Efficient Yield-Optimized Sizing Approach for Analog Circuits with Accurate Variation Consideration", IEEE International Workshop on Design for Manufacturability and Yield (DFM&Y), June 2012.
  • Kai-Hui Chang, Chia-Wei Chang, Jie-Hong Roland Jiang, and Chien-Nan Jimmy Liu, "Generating Local Test Point Activation Signals Using Controllability Don't-Cares", ACM/IEEE International Workshop on Logic and Synthesis (IWLS), June 2012.
  • Mu-Shun Matt Lee, Yi-Chu Liu, Wan-Rong Wu and Chien-Nan Jimmy Liu, "Peak Wake-up Current Estimation at Gate-level with Standard Library Information", IEEE International Symposium on VLSI Design, Automation, and Test (EI), April 2012.
  • Hsin-Yu Luo, Hsiu-Wen Li, Long-Ching Yeh, and Chien-Nan Jimmy Liu, "Automated Synthesis Design Flow of Power Converter Circuits Aimed at SOC Applications", IEEE International Symposium on Integrated Circuits (ISIC) (EI), December 2011.
  • Kai-Hui Chang, Chia-Wei Chang, Jie-Hong Roland Jiang, and Chien-Nan Jimmy Liu, "Improving Design Verifiability by Early RTL Coverability Analysis", ACM/IEEE International Workshop on Logic and Synthesis (IWLS), pp. 183-188, June 2011.
  • Mu-Shun Matt Lee, Wei-Ting Liao, Guan-Ming Zhu and Chien-Nan Jimmy Liu, "A High-Level Current Model for Macro Cells Using Dynamic Levelization Algorithm", IEEE International Symposium on VLSI Design, Automation, and Test (EI), pp. 1-4, April 2011.
  • Chia-Wei Chang, Hong-Zu Chou, Kai-Hui Chang, Jie-Hong Roland Jiang, Chien-Nan Jimmy Liu, Chiu-Han Hsiao and Sy-Yen Kuo, "Constraint Generation for Software-Based Post-Silicon Bug Masking with Scalable Resynthesis Technique for Constraint Optimization", IEEE International Symposium on Quality Electronic Design (ISQED), pp. 174-181, March 2011.
  • Chia-Jen Chang, Pao-Jen Huang, Tai-Chen Chen, and Chien-Nan Jimmy Liu, "ILP-Based Inter-Die Routing for 3D ICs", ACM/IEEE Asia and South Pacific Design Automation Conference (EI), pp. 330-335, January 2011.
  • Hsin-Yu Luo, Hsiu-Wen Li, Xiao-Qian Chang, and Chien-Nan Jimmy Liu, "On Behavioral Modeling for Sigma-Delta Digital-to-Analog Converters with Accurate Timing Response", the 16th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp. 84-89, October 2010.
  • Chin-Cheng Kuo, Yen-Lung Chen, I-Ching Tsai, Li-Yu Chan, and Chien-Nan Jimmy Liu, "Behavior-Level Yield Enhancement Approach for Large-Scaled Analog Circuits", IEEE/ACM Design Automation Conference (DAC) (EI), pp. 903-908, June 2010.
  • Mu-Shun Matt Lee, Kuo-Sheng Lai, Chia-Ling Hsu, and Chien-Nan Jimmy Liu, "Dynamic IR Drop Estimation at Gate Level with Standard Library Information", IEEE International Symposium on Circuit and Systems (EI), pp. 2606-2609, May 2010.
  • Hsiu-Wen Li, Ren-Hong Fu, Hsin-Yu Luo, and Chien-Nan Jimmy Liu, "Automatic Circuit Adjustment Technique for Process Sensitivity Reduction and Yield Improvement", IEEE International Symposium on Circuit and Systems (EI), pp. 2582-2585, May 2010.
  • Sung-Che Li, Wei-Ting Liao, Mu-Shun Lee, Wen-Tsan Hsieh and Chien-Nan Jimmy Liu, "A Practical Power Model of AMBA System for High-Level Power Analysis", IEEE International Symposium on VLSI Design, Automation, and Test (EI), pp. 347-350, April 2009.
  • Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu, and Wen-Yu Shih, "Package Routability- and IR-Drop-Aware Finger/Pad Assignment in Chip-Package Co-Design", IEEE/ACM Design, Automation & Test in Europe (DATE) (EI), pp. 845-850, April 2009.
  • Pao-Jen Huang, Wei-Hsiang Cheng, and Chien-Nan Jimmy Liu, "Efficient State Space Enumeration for the Verification of Analog Designs", the 15th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp. 410-415, March 2009.
  • Chin-Cheng Kuo, Pei-Syun Lin, and Chien-Nan Jimmy Liu, "A SCORE Macromodel for PLL Designs to Analyze Supply Noise Interaction Issues at Behavioral Level", ACM/IEEE Asia and South Pacific Design Automation Conference (EI), pp. 516-521, January 2009.
  • Hungwen Lu, ChauChin Su, and Chien-Nan Liu, "A Scalable Digitalized Buffer for Gigabit I/O", IEEE Custom Integrated Circuits Conference (EI), pp. 241-244, September 2008.
  • Mu-Shun Lee, Chin-Hsun Lin, Chien-Nan Jimmy Liu, and Shih-Che Lin, "Quick Supply Current Waveform Estimation at Gate Level Using Existed Cell Library Information", ACM/IEEE Great Lakes Symposium on VLSI (EI), pp. 135-138, May 2008.
  • Wen-Tsan Hsieh, Hsin-Ying Liao, Chien-Nan Jimmy Liu, Shu-Yu Cheng, and Ji-Jan Chen, "Pipeline-Aware Instruction-Level Power Analysis for VLIW DSP Core", the 14th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp. 495-499, October 2007.
  • Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu, and Wen-Yu Shih, "An I/O Planning Method for Three-Dimensional Integrated Circuits", the 14th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp. 198-202, October 2007.
  • Chi-Yi Yeh, Hung-Ming Chen, Li-Da Huang, Wei-Ting Wei, Chao-Hung Lu, and Chien-Nan Liu, "Using Power Gating Techniques in Area-Array SoC Floorplan Design", IEEE International SoC Conference, pp. 233-236, September 2007.
  • Chin-Cheng Kuo, Meng-Jung Lee, I-Ching Tsai, Chien-Nan Jimmy Liu, and Ching-Ji Huang, "An Accurate PLL Behavioral Model for Fast Monte Carlo Analysis under Process Variation", IEEE International Workshop on Behavioral Modeling and Simulation, pp. 110-114, September 2007.
  • Wei-Hsiang Cheng, Chin-Cheng Kuo, Po-Jen Chen, Yi-Min Wang, and Chien-Nan Jimmy Liu, "An Efficient Bottom-Up Extraction Approach to Build the Behavioral Model of Switched-Capacitor Sigma-Delta Modulator", IEEE International Workshop on Behavioral Modeling and Simulation, pp. 17-21, September 2007.
  • Chao-Hung Lu, Hung-Ming Chen, and Chien-Nan Jimmy Liu, "On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design", ACM/IEEE Asia and South Pacific Design Automation Conference (EI), pp. 792-797, January 2007.
  • Chao-Hung Lu, Hung-Ming Chen, and Chien-Nan Jimmy Liu, "On Achieving Better Signal Integrity in Area-Array Floorplanning by Minimal Decap Insertion", International Computer Symposium, pp. 68-73, December 2006.
  • Chin-Cheng Kuo and Chien-Nan Jimmy Liu, "On Efficient Behavioral Modeling to Accurately Predict Supply Noise Effects of PLL Designs in Real Systems", IFIP International Conference on Very Large Scale Integration, pp. 116-121, October 2006.
  • Wen-Tsan Hsieh, Chi-Chia Yu, Chien-Nan Jimmy Liu, and Yi-Fang Chiu, "A Scalable Power Modeling Approach for Embedded Memory Using LIB Format", International Workshop on Power and Timing Modeling, Optimization and Simulation, pp. 543-552, September 2006.
  • Wei-Hsiang Cheng, Chin-Lung Chuang, and Chien-Nan Jimmy Liu, " An Efficient Mechanism to Provide Full Visibility for Hardware Debugging", IEEE International Symposium on Circuit and Systems (EI), pp. 811-814, May 2006.
  • Chin-Cheng Kuo and Chien-Nan Jimmy Liu, "Accurate Behavioral Modeling Approach for PLL Designs with Supply Noise Effects", IEEE International Workshop on Behavioral Modeling and Simulation, pp. 48-53, September 2005.
  • Wen-Tsan Hsieh, Chih-Chieh Shiue, and Chien-Nan Jimmy Liu, " A Novel Approach for High-Level Power Modeling of Sequential Circuits Using Recurrent Neural Networks", IEEE International Symposium on Circuit and Systems (EI), pp. 3591-3594, May 2005.
  • Tai-Ying Jiang, Chien-Nan Jimmy Liu, and Jing-Yang Jou, " Estimating Likelihood of Correctness for Error Candidates to Assist Debugging Faulty HDL Designs", IEEE International Symposium on Circuit and Systems (EI), pp. 5682-5685, May 2005.
  • Wen-Tsan Hsieh, Chien-Nan Jimmy Liu, Yao-Feng Wang, and Yi-Fang Chiu, " An Efficient Power Modeling Approach for Embedded Memory Using LIB Format", IEEE International Symposium on VLSI Design, Automation, and Test (EI), pp. 55-58, April 2005.
  • Chin-Cheng Kuo, Yu-Chien Wang, and Chien-Nan Jimmy Liu, "An Efficient Bottom-Up Extraction Approach to Build Accurate PLL Behavioral Models for SOC Designs", ACM/IEEE Great Lakes Symposium on VLSI (EI), pp. 286-290, April 2005.
  • Tai-Ying Jiang, Chien-Nan Jimmy Liu, and Jing-Yang Jou, " An Observability Measure to Enhance Statement Coverage Metric for Proper Evaluation of Verification Completeness ", ACM/IEEE Asia and South Pacific Design Automation Conference (EI), pp. 323-326, January 2005.
  • Chin-Lung Chuang, Dong-Jung Lu, and Chien-Nan Jimmy Liu, " A Snapshot Method to Provide Full Visibility for Functional Debugging Using FPGA ", The 13th IEEE Asia Test Symposium (EI), pp. 164-169, November 2004.
  • Yuan-Bin Sha, Mu-Shun Lee and Chien-Nan Jimmy Liu, " On Code Coverage Measurement for Verilog-A ", IEEE International High-Level Design Validation and Test Workshop (HLDVT'04), pp. 115-120, November 2004.
  • Bao-Ren James Huang, Tzung-Jr Karger Tsai, and Chien-Nan Jimmy Liu, "On Debugging Assistance in Assertion-Based Verification", the 12th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI 2004), pp. 290-295, October 2004.
  • Chih-Yang Hsu, Chien-Nan Jimmy Liu, and Jing-Yang Jou, " Improved Vector Compaction for Power Estimation with Multi-Sequence Sampling Technique ", IEEE International Symposium on VLSI Technology, Systems, and Applications (EI), pp. 176-179, October 2003.
  • Chien-Nan Jimmy Liu, "A Design-for-Verification Technique for Reducing Debugging Efforts in HDL", the Eleventh Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI 2003), pp. 33-38, April 2003.
  • Chih-Yang Hsu, Chien-Nan Jimmy Liu, and Jing-Yang Jou, " An Efficient IP-Level Power Model for Complex Digital Circuits ", ACM/IEEE Asia and South Pacific Design Automation Conference (EI), pp. 610-613, January 2003.
  • Tai-Ying Jiang, Chien-Nan Jimmy Liu and Jing-Yang Jou, " Error Diagnosis for RTL Designs in HDLs ", The 11th IEEE Asia Test Symposium (EI), pp. 362-367, November 2002.
  • Chien-Nan Jimmy Liu, Chia-Chih Yen, and Jing-Yang Jou, "Automatic Functional Vector Generation Using the Interacting FSM Model", IEEE International Symposium on Quality Electronic Design (ISQED 2001), pp. 372-377, March 2001.
  • Chien-Nan Jimmy Liu, I-Ling Chen, and Jing-Yang Jou, "An Efficient Design-for-Verification Technique for HDLs", ACM/IEEE Asia and South Pacific Design Automation Conference (EI), pp. 103-108, January 2001.
  • Chien-Nan Jimmy Liu, Chen-Yi Chang, Jing-Yang Jou, Ming-Chih Lai, and Hsing-Ming Juan, "A Novel Approach for Functional Coverage Measurement in HDL", IEEE International Symposium on Circuit And Systems (EI), vol. 4, pp. 217-220, May 2000.
  • Chien-Nan Jimmy Liu and Jing-Yang Jou, "An Efficient Functional Coverage Test for HDL Descriptions at RTL", IEEE International Conference on Computer Design (EI), pp. 325-327, October 1999.
  • Jing-Yang Jou and Chien-Nan Jimmy Liu, " Coverage Analysis Techniques for HDL Design Validation ", the 6th Asia Pacific Conference on cHip Design Languages (APCHDL'99), pp. 3-10, October 1999. (Invited Paper)
  • Chien-Nan Liu and Jing-Yang Jou, " A FSM Extractor for HDL Descriptions at RTL ", the 5th Asia Pacific Conference on Hardware Description Languages (APCHDL'98), June 1998.
  • Domestic Conference Proceedings

  • Hao-Yu Chi, Han-Chung Chang, Chien-Nan Jimmy Liu, and Hung-Ming Chen, "On Global Routing Estimation for Analog Placement", the 32nd VLSI Design/CAD Symposium, Taiwan, August 2021.
  • Shih-Han Chang, Alexandra Küster, and Chien-Nan Jimmy Liu, "Coupling-Aware Behavioral Modeling for the Verification of In-Memory Computing Design in AI Edge Applications", the 32nd VLSI Design/CAD Symposium, Taiwan, August 2021.
  • Hao-Yu Chi, Chih-Hsin Yang, Wei-Hsiang Chou, Chien-Nan Jimmy Liu, Hung-Ming Chen, and Jing-Yang Jou, "Bending-Aware Analog Layout Migration Methodology", the 31st VLSI Design/CAD Symposium, Taichung, Taiwan, August 2020.
  • Ming-Hung Wang, Tung-Chieh Kuo, and Chien-Nan Jimmy Liu, "A DNN-Assisted Evolutionary Algorithm for Analog Circuit Sizing", the 31st VLSI Design/CAD Symposium, Taichung, Taiwan, August 2020.
  • Ling-Yen Song, Yu-Kai Chang, Han-Chung Chang, Chien-Nan Liu, Jing-Yang Jou, Yun-Jing Lin and Meng-Jung Lee, "A Current-Based Partition Approach for Multiple Sub-Circuit Identification in Mixed-Signal Circuits", the 30th VLSI Design/CAD Symposium, Kaohsiung, Taiwan, August 2019.
  • Zi-Jun Lin, Chih-Hsin Yang, Hao-Yu Chi, Chien-Nan Jimmy Liu, and Jing-Yang Jou, "A SP-Based Analog Layout Migration Engine for Placement Preservation", the 30th VLSI Design/CAD Symposium, Kaohsiung, Taiwan, August 2019.
  • Hao-Yu Chi, Yuan-Heng Hsu, Yu-Hsien Chen, Chien-Nan Jimmy Liu and Hung-Ming Chen, "Performance-Preserved Analog Routing Methodology Considering Matching Constraints", the 29th VLSI Design/CAD Symposium, Tainan, Taiwan, August 2018.
  • Yu-Hsuan Kuo, Si-Rong He, Meng-Lin Li, Ji-Xuan Tsai, Chien-Nan Jimmy Liu, and Jing-Yang Jou, "Efficient Lifetime Yield Analysis with Analog Behavioral Models", the 29th VLSI Design/CAD Symposium, Tainan, Taiwan, August 2018.
  • Yu-Kang Lou, Chi-Lien Kuo, Zi-Jun Lin, Yu-Kai Chang, Chien-Nan Liu, Jing-Yang Jou, Yun-Jing Lin and Meng-Jung Lee, "Fast Recognition of Digital Blocks in Mixed-Signal Circuits", the 29th VLSI Design/CAD Symposium, Tainan, Taiwan, August 2018.
  • Yu-Yun Lin, Chia-Hao Hung, Hwa-Yi Tseng, Chien-Nan Jimmy Liu, "Design Automation for Sub-Threshold Operational Amplifier Circuits", the 28th VLSI Design/CAD Symposium, Kenting, Taiwan, August 2017.
  • Sheng-Ying Pan, Hao-Yu Chang, Ji-Xuan Tsai, Chien-Nan Jimmy Liu, and Jing-Yang Jou, "A New Adaptor for WDF-Based Analog Emulator with Complicated Topology", the 28th VLSI Design/CAD Symposium, Kenting, Taiwan, August 2017.
  • Chang-Han Wang, Sheng-Ying Pan, Loo-Shean Liu, Chien-Nan Jimmy Liu, and Jing-Yang Jou, "Nonlinear MOS Model for WDF-Based Analog Emulators", the 27th VLSI Design/CAD Symposium, Kaohsiung, Taiwan, August 2016.
  • Fang-Yu Jhou, Si-Rong He, Ching-Ho Lin, and Chien-Nan Jimmy Liu, "Automated CMOS Voltage Rectifier Design with Impedance Consideration", the 26th VLSI Design/CAD Symposium, Hualien, Taiwan, August 2015.
  • Chien-Hung Ho, Ming-You Li, Yu-Yun Lin, and Chien-Nan Jimmy Liu, "Efficient Worst Case Identification Method for PVT Corner Analysis", the 26th VLSI Design/CAD Symposium, Hualien, Taiwan, August 2015.
  • Yen-Lung Chen, Wei Wu, Chien-Nan Jimmy Liu, and Lei He, "Stochastic Behavioral Modeling of Analog Circuits with Reliability", the 25th VLSI Design/CAD Symposium, Taichung, Taiwan, August 2014.
  • Wan-Chun Chen, Chien-Hung Ho, Long-Ching Yeh, and Chien-Nan Jimmy Liu, "Automatic Synthesis Flow of Current Mode Control DC-DC Buck Converter Circuits", the 24rd VLSI Design/CAD Symposium, Kaohsiung, Taiwan, August 2013.
  • Ju-Chi Hsu, Mu-Shun Matt Lee, Fang-Yu Jhou and Chien-Nan Jimmy Liu, "Estimation of Dynamic Simultaneous Switching Noise Using Advanced Standard Library Information", the 24rd VLSI Design/CAD Symposium, Kaohsiung, Taiwan, August 2013.
  • Yen-Lung Chen, Ya-Fang Cheng, Li-Yu Chan, Guan-Ruei Lu and Chien-Nan Jimmy Liu, "A Bias-Driven Approach for Efficient Analog Design Automation", the 23rd VLSI Design/CAD Symposium, Kenting, Taiwan, August 2012.
  • Yen-Lung Chen, Wan-Rong Wu, Hsing-Han Tseng and Chien-Nan Jimmy Liu, "Efficient Yield-Optimized Sizing Approach for the Analog Circuits with Flexible TFTs", the 23rd VLSI Design/CAD Symposium, Kenting, Taiwan, August 2012.
  • Li-Yu Chan, Ya-Fang Cheng, and Chien-Nan Jimmy Liu, "A Bias-Driven Approach to Reduce the Search Space in OPA Synthesis Procedure", the 22nd VLSI Design/CAD Symposium, Yunlin, Taiwan, August 2011.
  • Hsin-Yu Luo, Hsiu-Wen Li, Chih-Hsien Chang, Long-Ching Yeh, and Chien-Nan Jimmy Liu, "Power Converter Synthesis Flow for SOC Applications", the 22nd VLSI Design/CAD Symposium, Yunlin, Taiwan, August 2011.
  • Yen-Lung Chen, Pei-Syun Lin, Chia-Ling Hsu, Hsueh-Mou Wu, and Chien-Nan Jimmy Liu, "Process Sensitivity Reduction for Improving the Yield of CPPLL", The 21st VLSI Design/CAD Symposium, Kaohsiung, Taiwan, August 2010.
  • Ju-Chi Hsu, Mu-Shun Matt Lee, Wei-Ting Liao and Chien-Nan Jimmy Liu, "IP-Based High-Level Supply Current Model Using Dynamic Levelization Algorithm", The 21st VLSI Design/CAD Symposium, Kaohsiung, Taiwan, August 2010.
  • Chin-Cheng Kuo, I-Ching Tsai, Yen-Lung Chen, and Chien-Nan Jimmy Liu, "A Force-Directed Yield Enhancement Approach for PLL Circuits", The 20th VLSI Design/CAD Symposium, Hualien, Taiwan, August 2009.
  • Yi-Chu Liu, Mu-Shun Matt Lee, Hsin-Ying Liao, and Chien-Nan Jimmy Liu, "A Practical High-Level Current Model for Embedded SRAM", The 20th VLSI Design/CAD Symposium, Hualien, Taiwan, August 2009.
  • Pao-Jen James Huang, Wei-Hsiang Cheng, and Chien-Nan Jimmy Liu, "Formal State Transition Enumeration for Analog Verification", The 19th VLSI Design/CAD Symposium, Kenting, Taiwan, August 2008.
  • Sung-Che Li, Mu-Shun Lee, Wen-Tsan Hsieh, and Chien-Nan Jimmy Liu, "An Efficient Cycle-Accurate Power Analysis Methodology for AMBA System", The 19th VLSI Design/CAD Symposium, Kenting, Taiwan, August 2008.
  • Chin-Cheng Kuo, Meng-Jung Lee, I-Ching Tsai, Chien-Nan Jimmy Liu, and Ching-Ji Huang, "An Efficient BMCS Approach to Accurately Predict Process Variation Effects of PLL Circuits", The 18th VLSI Design/CAD Symposium, Hualien, Taiwan, August 2007.
  • Wen-Tsan Hsieh, Hsin-Ying Liao, Chien-Nan Jimmy Liu, Shu-Yu Cheng, and Ji-Jan Chen, "An Efficient Energy Modeling Approach for VLIW DSP at Instruction-Level", The 18th VLSI Design/CAD Symposium, Hualien, Taiwan, August 2007.
  • Chin-Cheng Kuo, and Chien-Nan Jimmy Liu, "Irregular Noise Aware Behavioral Models for PLL Circuits", The 17th VLSI Design/CAD Symposium, Hualien, Taiwan, August 2006.
  • Wenliang Tseng, Michel S. Nakhla, Yuhwai Tseng, Chien-Nan Jimmy Liu, and Chauchin Su, "Passive model order reduction algorithm for linear time-delay systems", The 16th VLSI Design/CAD Symposium, Hualien, Taiwan, August 2005.
  • Tsung-Chih Tsai, Chin-Lung Chuang, and Chien-Nan Jimmy Liu, "Assertion-Based Verification for Hardware Debugging", The 16th VLSI Design/CAD Symposium, Hualien, Taiwan, August 2005.
  • Chin-Cheng Kuo, Yu-Chien Wang, and Chien-Nan Jimmy Liu, "Accurate PLL Behavioral Models for IP-Based SOC Designs", The 16th VLSI Design/CAD Symposium, Hualien, Taiwan, August 2005.
  • Wen-Tsan Hsieh, Chih-Chieh Shiue, and Chien-Nan Jimmy Liu, "A Novel High-Level Power Model for Sequential Circuits", The 16th VLSI Design/CAD Symposium, Hualien, Taiwan, August 2005.
  • Yuan-Bin Sha and Chien-Nan Jimmy Liu, "The Study on Code Coverage Metrics for Verilog-A", The 15th VLSI Design/CAD Symposium, Kenting, Taiwan, August 2004.
  • Wen-Tsan Hsieh, Chih-Yang Hsu, Chien-Nan Jimmy Liu and Jing-Yang Jou, "A Novel Approach for High-Level Power Modeling with Neural Network", The 15th VLSI Design/CAD Symposium, Kenting, Taiwan, August 2004.
  • Chien-Nan Jimmy Liu and I-Ling Chen "A Design-for-Verification Technique for HDL Debugging", The 13rd VLSI Design/CAD Symposium, pp. 195-198, Tai-Dung, Taiwan, August 2002.
  • Tai-Ying Jiang, Chien-Nan Liu and Jing-Yang Jou, "Error Diagnosis for RTL Designs in HDLs", The 13rd VLSI Design/CAD Symposium, pp. 154-157, Tai-Dung, Taiwan, August 2002.
  • Chien-Nan Jimmy Liu and Jing-Yang Jou, "An Efficient Functional Test for FSMs in HDL Descriptions", The 10th VLSI Design/CAD Symposium, Nan-Tou, Taiwan, August 1999.
  • Chien-Nan Liu and Jing-Yang Jou, "FSM Recognition in HDL Descriptions ", The 9th VLSI Design/CAD Symposium, Nan-Tou, Taiwan, August 1998.
  • Others

  • Chien-Nan Liu, "On Computer-Aided Techniques for Functional Verification of Complex Digital Designs", Ph.D Dissertation, National Chiao Tung University, Taiwan, May 2001. ( PDF file, 4.8MB)
  • Patents

  • Yun-Jing Lin, Meng-Jung Lee, Yu-Lan Lo, Shu-Yi Kao, Chien-Nan Liu, Yu-Kang Lou, and Ching-Ho Lin, "Circuit Encoding Method and Circuit Structure Recognition Method", U.S. Patent No. 10,657,303, May 19, 2020.
  • 林筠菁,李孟蓉,羅幼嵐,高淑怡,劉建男,樓禹慷,林慶和,"電路編碼方法與電路架構的辨識方法", 中華民國發明專利 I-653543號, March, 2019.
  • Supervised Thesis

    Ph.D Dissertation

  • Hao-Yu Chi (紀浩瑜), September 2021, "Performance Oriented Automatic Analog Layout Synthesis Methodology".
  • Nguyen Cao Qui (阮貴曹), December 2017, "On the Applications of Delta Circuit Model for the Analysis of Process Variation and Aging Effects in Analog Circuits".
  • Yen-Lung Chen (陳彥龍), October 2014, "Automated Robust Design Optimization of Analog Circuits Considering Process Variations and Aging Effects".
  • Mu-Shun Lee (李牧勳), June 2012, "Front-End Supply Current Waveform Models for Dynamic IR-Drop Analysis".
  • Chin-Lung Chuang (莊青龍), December 2010, "Hybrid Testbench Acceleration with Full Visibility for Functional Verification ".
  • Chao-Hung Lu (呂昭宏), January 2010, "VLSI Design Planning with Power Integrity and I/O Constraints".
  • Chin-Cheng Kuo (郭晉誠), June 2009, "Bottom-up PLL Behavioral Modeling for Supply Noise Interactions and Yield Enhancement".
  • Wen-Tsan Hsieh (薛文燦), June 2007, "On High-Level Power Modeling Approaches for IP-Based SOC Designs".
  • Chih-Yang Hsu (許智揚), June 2005, "On Power Estimation Methods for Silicon Intellectual Properties".
  • Master Thesis
  • Tzu-Wen Huang (黃慈汶), September 2021, "A Study on PLL Implementation Using WDF-Based Circuit Emulator".
  • Yen-Chen Chung (鍾晏禎), August 2021, "Design Yield Analysis of SRAM-based System with Peripheral Circuits".
  • Wei-Xiang Chou (周暐翔), August 2021, "A Flexible Layout Migration Technique through Partial Learning".
  • Tung-Chieh Kuo (郭東杰), August 2021, "Fast Variation-aware Analog Circuit Sizing Approach with ML-Assisted Evolutionary Algorithm".
  • Shih-Han Chang (張詩涵), January 2021, "Coupling-Aware Behavioral Modeling for the Verification of In-SRAM Computing Design".
  • Han-Chung Chang (張瀚中), August 2020, "A Routing Methodology with Accurate Routing Resource Estimation for Analog Layout".
  • Ming-Hung Wang (王銘宏), August 2020, "On Machine-learning Assisted Evolutionary Algorithm with Parallel Computing for Analog Circuit Sizing".
  • Alexandra Küster (柯艾莉), July 2020, "High Accuracy Behavioral Modeling of In-Memory Computing Design for AI Edge Applications".
  • Yuan-Heng Xu (許元亨), July 2020, "On SRAM Power Model for In Memory Computing".
  • Zi-Jun Lin (林姿君), July 2019, "A Style-based Analog Layout Migration with Routing Behavior Preservation Technique".
  • Yu-Hsien Chen (陳宇嫻), July 2019, "An Analog Layout Generator with Structure-Based Methodology".
  • Ji-Xuan Tsai (蔡季軒), July 2019, "On WDF Structure Synthesis and Simulation for Analog Circuit Emulation".
  • Chia-Hao Hung (洪嘉壕), July 2018, "Analog Layout Migration Considering Routing Preservation with CDL-based R-tree".
  • Chi-Lien Kuo (郭啟鍊), July 2018, "Correct Recognition of Building Blocks in Mixed-Signal Circuits Based on Machine Learning Model".
  • Yu-Hsuan Kuo (郭語璇), July 2018, "Efficient Lifetime Yield Analysis with Analog Behavioral Models".
  • Hwa-Yi Tseng (曾華逸), July 2018, "Routing Cost Prediction at Placement Stage Using Machine Learning Technique".
  • Hsin-Ju Hsu (許昕茹), July 2017, "Automatic Layout Synthesis Tool for DC-DC Current-Mode Buck Converter".
  • Ling-Yen Song (宋伶彥), July 2017, "Non-Regression Calibration Approach for Analog Behavioral Model Generator".
  • Hao-Yu Chi (紀浩瑜), July 2017, "On Minimizing Wire Load of Analog Routing for Performance".
  • Sheng-Ying Pan (潘聖瑩), July 2017, "A New Adaptor for WDF-Based Analog Emulator with Complicated Topology".
  • Ming-You Li (李明祐), May 2017, "Hardware Implementation of Analog Emulator Based on Wave Digital Filters".
  • Yu-Yun Lin (林郁芸), May 2017, "Design Automation for Sub-Threshold Operational Amplifier Circuits".
  • Si-Rong He (何思蓉), January 2017, "An incremental simulation technique based on delta model for lifetime yield analysis".
  • Ching-Ho Lin (林慶和), September 2016, "Analytical Behavioral Model Generator for Analog Circuit Blocks with Digitalized Modeling Technique".
  • Hsu-Ping Yang (楊旭平), July 2016, "Automatic Construction and Scheduling of the Wave Digital Filter Structures for Analog Emulators".
  • Chih-Wei Lee (李致緯), July 2016, "Three-Level Hierarchical B*-Trees for Layout Optimization of High-Voltage VLSI Circuits".
  • Conan Yeh (葉生元), July 2015, "Timing and Resource Optimization of Pipelined Analog Emulator Based on Wave Digital Filters".
  • Jian-Yu Chen (陳建宇), July 2015, "Regression-Based Behavioral Model Generator for Analog Circuit Blocks".
  • Chien-Hung Ho (何建宏), July 2014, "Efficient Worst Case Identification Method for PVT Corner Analysis and Monte Carlo Simulation".
  • Hsing-Ju Chang (張馨如), July 2014, "Automatic Synthesis Tool for Low Dropout Regulator Considering Process Variations and Layout Effects".
  • Ying-Chi Lien (連映琦), July 2014, "Automatic Analog Synthesis Platform for Bio-signal Acquisition System".
  • Shiou-Wen Wang (王 糸秀 文), July 2014, "Automatic Behavioral Model Generation for Circuit Blocks in Mixed-Signal Designs".
  • Fang-Yu Jhou (周芳瑜), July 2014, "Automated CMOS Voltage Rectifier Design and Layout with Power and Impedance Consideration".
  • Hsing-Han Tseng (曾星翰), July 2013, "Global Equation-Based Design Space Reduction Method for Efficient Simulation-Based Optimization".
  • Guan-Ruei Lu (盧冠睿), July 2013, "Adaptive PVT Corner Analysis for Efficient Worst Case Identification".
  • Yu-Ching Liao (廖于晴), July 2013, "A Layout-Aware Analog Synthesis Environment on Laker".
  • Yun-Jing Lin (林筠菁), July 2013, "A Generic Behavior Model Generator for Interface Circuits with Graphical User Interface".
  • Wan-Chun Chen (陳宛君), January 2013, "Automatic Synthesis Flow of Current Mode Control DC-DC Buck Converter Circuits".
  • Guan-Ming Chu (朱冠銘), July 2012, "Simultaneous Optimization Approach for Low Dropout Regulator and Its Error Amplifier".
  • Chih-Hsien Chang (張志賢), July 2012, "Automatic Synthesis Flow of Switching Step-Up Converter Circuits".
  • Ya-Fang Cheng (鄭雅芳), July 2012, "A Bias-Driven OP-Amp Sizing Approach with Improved Prediction of Frequency Response and Channel Length Effect".
  • Yi-Ching Ding (丁宜菁), July 2012, "Template-Based Parasitic-Aware Synthesis Approach for Analog Circuits".
  • Wan-Rong Wu (吳宛蓉), July 2012, "Fast Reliability-Aware Automatic Sizing Approach for the Analog Circuits with Flexible TFTs".
  • Li-Yu Chan (詹立宇), July 2011, "A Bias-Driven Approach to Improve the Accuracy of GP-Based CMOS OP-Amp Design Automation".
  • Hsin-Yu Luo (羅欣瑜), July 2011, "Automatic Synthesis Flow of DC to DC Step-Down Converter Circuits".
  • Hsueh-Mou Wu (吳學謀), July 2011, "Thermal-Driven Floorplanning for 3D IC Using Fusion of Thermal-TSV Area".
  • Ju-Chi Hsu (許茹棋), July 2011, "On Dynamic Simultaneous Switching Noise Analysis with Advanced Standard Library Information".
  • Chia-Ling Hsu (許家綾), July 2011, "A Template-Based Layout Automation Tool for PLL Circuits".
  • Yen-Lung Chen (陳彥龍), July 2010, "An Enhanced Yield Optimization Approach for CPPLL via Process Sensitivity Reduction".
  • Yi-Chu Liu (劉奕初), July 2010, "Maximum Wake-up Current Estimation at Gate-level with Standard Library Information".
  • Pei-Syun Lin (林佩勳), July 2009, "On Sensitivity Reduction for Charge-Pump PLLs under Process Variation".
  • Ren-Hong Fu (傅仁弘), July 2009, "Automatic Process Sensitivity Reduction for OTA Circuits".
  • Chia-Jen Chang (張佳仁), July 2009, "Micro-Bump Assignment and Inter-Die Routing for 3D ICs".
  • Wei-Ting Liao (廖偉廷), July 2009, "A High-Level Neural Current Model Using Dynamic Levelization Algorithm".
  • Kuo-Sheng Lai (賴國勝), July 2009, "Gate-Level Supply Current Waveform Estimation for Dynamic IR-Drop Analysis with Standard Library Information".
  • Feng-Yi Huang (黃鳳儀), July 2009, "OP Amplifier Layout Automation with Laker".
  • Xiao-Qian Chang (張曉倩), January 2009, "On Behavioral Modeling for Sigma-Delta Digital to Analog Converter with Accurate Timing Response".
  • I-Ching Tsai (蔡宜青), July 2008, "A Boundary-less Design Centering Approach Using Statistical Yield Analysis Results for PLL Circuits".
  • Wen-Yu Shih (施文郁), July 2008, "Optimal Pad Assignment for Two-Layer BGA Package Using Chip-Package Co-Design".
  • Hsin-Ying Liao (廖心瑩), July 2008, "High-Level Current Modeling for Embedded SRAM".
  • Chin-Hsun Lin (林志勳), July 2008, "High-level IR-drop Estimation Based on Macro-level Current Waveform".
  • Sung-Che Li (李松哲), December 2007, "An Efficient Cycle-Accurate Power Analysis Methodology for AMBA System".
  • Meng-Jung Lee (李孟蓉), July 2007, "An Accurate PLL Behavioral Model for Fast Monte Carlo Analysis under Process Variation".
  • Po-Jen Chen (陳柏仁), July 2007, "On Behavioral Modeling of Switched-Capacitor Circuits with Non-Ideal Effects and Accurate Timing Response".
  • Yen-Ting Chao (趙彥廷), July 2007, "An Automation Flow of OP Amplifier Design with Accurate Behavior Model".
  • You-Cheng Yang (楊侑承), July 2006, "High-Level Current Macro Model Using Neural Network".
  • Chi-Chia Yu (游智嘉), July 2006, "A Scalable Power Modeling Approach for Embedded Memory Using LIB Format".
  • Yu-Hsin Lin (林育信), July 2006, "An Efficient Mechanism to Provide Full Visibility for Embedded Memory in FPGA".
  • Meng-Fan Liu (劉孟帆), June 2006, "On Analog Behavioral Modeling for Sigma-Delta DAC with Non-Ideal Effects".
  • Yi-Min Wang (王奕閔), June 2006, "On Behavioral Modeling for Second-Order Sigma-Delta Modulator Circuits with Non-Ideal Effects".
  • Shr-Je Lin (林士哲), July 2005, "On Current Waveform Estimation of Gate Level Designs Using Cell Library Information".
  • Hsiu-Wen Li (李修文), July 2005, "On Building Co-Simulation Platform for DVB-T Project".
  • Chin-Cheng Kuo (郭晉誠), July 2005, "Supply Noise Aware Behavioral Modeling for Phase-Locked Loop Circuits".
  • Tsung-Chih Tsai (蔡宗智), July 2005, "On Assertion-Based Verification for Hardware Debugging".
  • Wei-Hsiang Cheng (鄭偉翔), July 2005, "On Reducing Storage Data in the Snapshot Method for Hardware Debugging" .
  • Yuan-Bin Sha (夏源斌), July 2004, "The Study on Code Coverage Metrics for Verilog-A".
  • Chao-Hsi Wang (王朝曦), July 2004, "A Neural Current Model to Estimate the Current Waveform of Power/Ground Line".
  • Yu-Chien Wang (王裕謙), July 2004, "On Behavioral Modeling for Phase-Locked Loop Circuits with Non-Ideal Effects".
  • Bao-Ren Huang (黃保仁), June 2004, "On Debugging Assistance in Assertion-Based Verification".
  • Chih-Chieh Hsieh (薛智杰), June 2004, "On High-Level Power Model Using Recurrent Neural Network for Sequential Circuits".
  • Dong-Jung Lu (呂東榮), June 2004, "A Snapshot Method to Provide Full Visibility for Functional Debugging Using FPGA".
  • Ching-Ji Huang (黃清吉), July 2003, "On Back Annotation Process for the Behavioral Model of PLL Circuits".
  • Ching-Sun Lin (林慶舜), July 2003, "The Study on the Behavioral Model of IEEE 802.3 MAC Using SystemC Language".
  • Wen-Tsan Hsieh (薛文燦), June 2003, "A Novel High-Level Power Model Using Neural Network".
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